1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices and, more particularly, to the manufacture of flash memory devices and, more particularly, to the manufacture of flash memory devices on FDSOI substrates.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, application specific integrated circuits (ASICs) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors (FETs), wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer. Moreover, in many applications, flash memory devices comprising transistor devices are needed.
A flash memory (for example, a FLASH EPROM or FLASH EEPROM) is a semiconductor device that is formed from an array of memory cells (devices), with each cell having a floating gate transistor. Flash memory chips fall into two main categories, namely, those having a so-called “NOR” architecture and those having a so-called “NAND” architecture. Data can be written to each cell within the array, but the data is erased in blocks of cells. Each floating gate transistor comprises a source, a drain, a floating gate and a control gate. The floating gate uses channel hot electrons for writing from the drain and tunneling for erasure from the source. The sources of each floating gate in each cell in a row of the array are connected to form a source line. In embedded memory solutions, memory cells are provided in the neighborhood of logic devices and are, particularly, together with the logic devices on a single (monolithic) silicon substrate. Flash memory devices are used in many applications, including hand-held computing devices, wireless telephones and digital cameras, as well as automotive applications. To enable the individual memory elements of a flash memory chip to maintain the physical state with which they have been programmed, each memory region must be isolated from its neighboring regions, typically by shallow trench isolations.
A variety of single gate and split gate solutions for embedded memory cell architectures are known in the art. FIG. 1 illustrates, for exemplary purposes, an embedded super flash cell of the prior art. The cell is formed on a semiconductor substrate 11 wherein source/drain regions 12 are formed. The cell comprises a floating gate 13, a control gate 14, an erase gate 15 and a select gate 16 formed by a word line. All gates may be made of polysilicon and they are covered by a multilayer insulation structure 17. The multilayer insulation structure 17 comprises parts of spacer structures formed on the tops and sidewalls of the gates. The floating gate 13 is formed over a floating gate oxide layer 18 and it is separated from the erase gate 15 by a tunnel oxide layer 18a that may be formed of the same material as the floating gate oxide layer 18. The control gate 14 and the floating gate 13 are separated from each other by an isolation layer 19, for example, an oxide-nitride-oxide (ONO) layer provided in order to enhance the capacitive coupling between the floating gate 13 and the control gate 14.
However, whereas flash cell integration in the context of manufacturing of field effect transistors (FETs) with silicon-oxynitride gate dielectrics can be reliably achieved, integration of flash cells in CMOS technologies used for the formation of FETs (and, for example, comprising the formation of high-k metal gate transistor devices) still poses challenging problems. Particularly, in the context of Fully Depleted Silicon-On-Insulator (FDSOI) Complementary Metal-Oxide-Semiconductor (CMOS) manufacturing techniques, co-integration of non-volatile memory cells as flash memory cells requires many additional deposition and masking steps.
FIG. 2 shows a typical semiconductor device or integrated circuit product comprising a bulk transistor device 40 and an FDSOI transistor device 50. The bulk transistor device 40 and the FDSOI transistor device 50 are isolated from each other by some form of isolation region 60. The bulk transistor device 40 is formed on a semiconductor bulk substrate 41 that provides a channel region in a top region of the bulk substrate 41. The bulk transistor device 40 comprises a polysilicon gate electrode layer 42, a metal gate electrode layer 43, a work function adjusting layer 44 and a gate dielectric layer 45 that, for example, is a high-k dielectric layer. Furthermore, the bulk transistor device 40 comprises a sidewall spacer 46 and raised source/drain regions 47.
The FDSOI transistor device 50 is formed on an SOI substrate that comprises a semiconductor bulk substrate 51, a buried oxide layer 52 formed on the semiconductor bulk substrate 51 and a semiconductor layer 53 that provides a channel region of the FDSOI transistor device 50. Further, the FDSOI transistor device 50 comprises a polysilicon gate electrode layer 54, a metal gate electrode layer 55, a work function adjusting layer 56 and a gate dielectric layer 57 that, for example, is a high-k dielectric layer. A sidewall spacer 58 is formed at sidewalls of the above-mentioned layers and raised source/drain regions 59 are formed by epitaxy on the surface of the semiconductor layer 53. The process flow of manufacturing the semiconductor device shown in FIG. 2 can be optimized with respect to the number of mask layers, etching processes, implantation processes, etc. However, in the prior art, the integration of the manufacture of flash memory devices in that process flow requires additional deposition and masking steps, thereby significantly increasing the complexity of the overall processing and manufacturing costs.
In view of the situation described above, the present disclosure provides a technique of forming a semiconductor device comprising a flash memory device integrated within (FD)SOI technologies with a reduced number of processing steps as compared to the art. In addition, a semiconductor device comprising a flash memory device formed according to a method of manufacturing in accordance with the present disclosure is provided.